Design for Test Engineer
Apple
- Location
- Onsite (Austin, Texas)
- Employment
- Full-time
- Level
- Mid Level
Posted 1 week ago
About the role
Apple is seeking a Design for Test Engineer in Austin to lead scan insertion and ATPG pattern generation. This role involves collaborating with cross-functional teams to resolve hardware design issues and developing infrastructure to improve design cycles and quality.
Skills
Verilog
RTL
DFT
ATPG
Python
Perl
TCL
CDC
RDC
Lint
Synthesis
Scan insertion
MBIST
STA
SOC development
Hardware design
Full job details
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APPLE INC has the following available in Austin, Texas. Responsible for scan insertion and ATPG (Automatic Pattern Generation) during the DFT design development phase which involves collaborating with different cross functional teams (DV, Front-End, PD and STA team) on solving hardware design issues. Deliver collaterals (configs and scripts) which are used by the Front-end team during RTL generation for scan insertion. Debug and provide support to Front-end team to tackle challenges and ensure high quality of scan insertion in the design during synthesis. Support the PD, STA and DV team on issues faced due to scan insertion. Ensure high quality of pattern generation and achieve higher stuck-at coverage, using ATPG tool, by maintaining and improving ATPG flows. Work with CAD team and tool vendor to resolve issues and improve flows. Debug simulation and silicon failures and solve issues through RTL, script, or configuration changes. Generate patterns at partition-level and top-level and make sure that they achieve targeted coverage according to project specifications. Create infrastructure to improve the design cycle and to implement new checks to catch more RTL issues early in the design cycle. Meet the deadlines of projects and deliver high quality results. Implement DFT infrastructure to maintain high quality results while working with the DV team to verify DFT implementations and implement ECOs. Ensure compliance with specifications and codes by working with designers on STA, physical, power and logical issues. 40 hours/week.
Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation. Experience and/or education must include: Utilizing Verilog to write RTL for DFT IP Utilizing RTL Design for DFT features such as scan codec, ATPG isolation, and scan routing Utilizing Scripting language (Python, Perl, or TCL) including automation of design flows, verification, synthesis and modeling Utilizing basic FE tools (CDC, RDC, Lint) with understanding of clock and reset domain and error resolution Utilizing synthesis tools and setting up of constraints and configurations for synthesis Utilizing ATPG tools for Scan DRC (w/error resolution) and ATPG coverage (w/analysis and improvement) Utilizing computer architecture principles and basic SOC development flows to allow for productive DFT analysis and debug Utilizing Scan and MBIST DFT architecture and implementation concepts to enable effective DFT implementation
N/A
Description
APPLE INC has the following available in Austin, Texas. Responsible for scan insertion and ATPG (Automatic Pattern Generation) during the DFT design development phase which involves collaborating with different cross functional teams (DV, Front-End, PD and STA team) on solving hardware design issues. Deliver collaterals (configs and scripts) which are used by the Front-end team during RTL generation for scan insertion. Debug and provide support to Front-end team to tackle challenges and ensure high quality of scan insertion in the design during synthesis. Support the PD, STA and DV team on issues faced due to scan insertion. Ensure high quality of pattern generation and achieve higher stuck-at coverage, using ATPG tool, by maintaining and improving ATPG flows. Work with CAD team and tool vendor to resolve issues and improve flows. Debug simulation and silicon failures and solve issues through RTL, script, or configuration changes. Generate patterns at partition-level and top-level and make sure that they achieve targeted coverage according to project specifications. Create infrastructure to improve the design cycle and to implement new checks to catch more RTL issues early in the design cycle. Meet the deadlines of projects and deliver high quality results. Implement DFT infrastructure to maintain high quality results while working with the DV team to verify DFT implementations and implement ECOs. Ensure compliance with specifications and codes by working with designers on STA, physical, power and logical issues. 40 hours/week.
Minimum Qualifications
Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation. Experience and/or education must include: Utilizing Verilog to write RTL for DFT IP Utilizing RTL Design for DFT features such as scan codec, ATPG isolation, and scan routing Utilizing Scripting language (Python, Perl, or TCL) including automation of design flows, verification, synthesis and modeling Utilizing basic FE tools (CDC, RDC, Lint) with understanding of clock and reset domain and error resolution Utilizing synthesis tools and setting up of constraints and configurations for synthesis Utilizing ATPG tools for Scan DRC (w/error resolution) and ATPG coverage (w/analysis and improvement) Utilizing computer architecture principles and basic SOC development flows to allow for productive DFT analysis and debug Utilizing Scan and MBIST DFT architecture and implementation concepts to enable effective DFT implementation
Preferred Qualifications
N/A