Design for Test Engineer
Apple
- Location
- Onsite (Cupertino, California)
- Compensation
- $174k - $225k/yr
- Employment
- Full-time
- Level
- Mid Level
Posted 4 days ago
About the role
Apple is seeking a Design for Test Engineer to develop verification plans and implement test benches for Analog IPs and DFT features. The role involves collaborating with designers to ensure design quality through RTL and gate-level simulations.
Skills
VLSI Design
VLSI Architecture
Verilog
Perl
Python
Tcl
CMOS
Digital Logic Gate Analysis
Test Automation
Timing Analysis
Synthesis
Simulation
DFT
ATE
Memory Circuits
RTL
Benefits
- Medical coverage
- Dental coverage
- Retirement benefits
Perks
- Employee stock programs
- Tuition reimbursement
- Discounted products
Full job details
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino , California and various unanticipated locations throughout the USA. Review Architecture and Design Specifications. Extract design features and develop attributes and verification plans. Work with designers to verify DFT implementation and run various checks. Implement test benches, assertions, checkers, generating directed/constrained random tests. Debug failures, run RTL simulations/power aware gate level simulations, supervise bugs, and close coverage. Build custom testbenches with power aware designs. Generate Collaterals and reports for the test. Perform simulations in RTL, Gate Netlist, and with X-propagation and UPF enabled. Generate Pattern files with DV test scripts. Run playback simulations with the generated patterns. Handle schedules and support multi-functional engineering effort. Assist in verification flows, automation scripts and regressions. Work with test engineers to bring up functional and structural patterns for various Analog IPs and DFT features on Silicon and support further characterization and test time optimization. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 1 year of experience in the job offered or related occupation. Experience and/or education must include: Utilizing VLSI Design and VLSI Architecture to understand complex ASIC designs Using Computer Architecture to aid in understanding of compute Using Verilog skills to debug and verify designs Using Perl/Python/Tcl scripting to aid in automating scripts and internal tools CMOS devices and circuits Using Digital Logic Gate Analysis and Design Using Test Automation and Test Methodology Performing Timing Analysis to debug complex timing bugs Employing Synthesis and Simulation to debug RTL and netlist issues Utilizing DFT knowledge for generating ATE patterns and ATE debug Verifying memory operation behavior using knowledge of Memory Circuits
N/A
Description
APPLE INC has the following available in Cupertino , California and various unanticipated locations throughout the USA. Review Architecture and Design Specifications. Extract design features and develop attributes and verification plans. Work with designers to verify DFT implementation and run various checks. Implement test benches, assertions, checkers, generating directed/constrained random tests. Debug failures, run RTL simulations/power aware gate level simulations, supervise bugs, and close coverage. Build custom testbenches with power aware designs. Generate Collaterals and reports for the test. Perform simulations in RTL, Gate Netlist, and with X-propagation and UPF enabled. Generate Pattern files with DV test scripts. Run playback simulations with the generated patterns. Handle schedules and support multi-functional engineering effort. Assist in verification flows, automation scripts and regressions. Work with test engineers to bring up functional and structural patterns for various Analog IPs and DFT features on Silicon and support further characterization and test time optimization. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Minimum Qualifications
Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 1 year of experience in the job offered or related occupation. Experience and/or education must include: Utilizing VLSI Design and VLSI Architecture to understand complex ASIC designs Using Computer Architecture to aid in understanding of compute Using Verilog skills to debug and verify designs Using Perl/Python/Tcl scripting to aid in automating scripts and internal tools CMOS devices and circuits Using Digital Logic Gate Analysis and Design Using Test Automation and Test Methodology Performing Timing Analysis to debug complex timing bugs Employing Synthesis and Simulation to debug RTL and netlist issues Utilizing DFT knowledge for generating ATE patterns and ATE debug Verifying memory operation behavior using knowledge of Memory Circuits
Preferred Qualifications
N/A