Design for Test Engineer
Apple
- Location
- Onsite (Cupertino, California)
- Employment
- Full-time
- Level
- Mid Level
Posted 2 days ago
About the Role
Apple is seeking a Design for Test Engineer to own the development design of large SOC blocks, including IP integration and system bus logic. This role involves collaborating with multi-disciplinary teams to ensure high-quality designs are delivered on time for first tapeout success.
Skills
ASIC Design Flow
RTL Design
DFT Insertion
Synthesis
Timing Closure
SOC IP Integration
Design Verification
Netlist Generation
CDC
Logical Equivalence
UPF Flow
Scripting
Low Power Design
Chip Architecture
Physical Design
System Bus Logic
Full job details
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Apple is looking for a talented and motivated Design for Test Engineer to be apart of a highly talented team. You will be at the heart of the chip design effort collaborating with all disciplines (vertical product model) with critical impact in getting functional products to millions of customers quickly.
As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Apple is looking for a talented and motivated Design Verification Engineer to be part of a highly talented team. You will be at the heart of the chip design effort collaborating with all disciplines (vertical product model) with critical impact in getting functional products to millions of customers quickly.
Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing closure for the block Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs Develop and maintain methodology/flows/checks for your design Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process
BSEE/MSEE, MSCE, or PhD program
Knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation Proven track record of high performance designs for low power applications, RTL design and timing closure on large complex designs SOC IP integration and RTL Design for performance, low area, and low power FE synthesis with DFT insertion ASIC design flow and netlist flow checks - CDC, Logical Equivalence UPF flow for power islands as well as voltage islands Familiarity with DFT and backend related methodology and tools is a plus
Description
Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing closure for the block Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs Develop and maintain methodology/flows/checks for your design Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process
Minimum Qualifications
BSEE/MSEE, MSCE, or PhD program
Preferred Qualifications
Knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation Proven track record of high performance designs for low power applications, RTL design and timing closure on large complex designs SOC IP integration and RTL Design for performance, low area, and low power FE synthesis with DFT insertion ASIC design flow and netlist flow checks - CDC, Logical Equivalence UPF flow for power islands as well as voltage islands Familiarity with DFT and backend related methodology and tools is a plus